In order to explain the background of the present invention in detail, reference will be made to FIG. 1, which shows a circuit diagram of a prior art semiconductor memory device. There are provided enhancement type MOS field-effect transistors 1,2,3 and 4, hereinafter referred to as MOSFETs. The drains of the P-channel MOSFET 1 and N-channel MOSFET 2 are connected to each other, and the gates thereof are connected to each other. The source of the MOSFET 1 is connected to a power supply terminal 5, and that of the MOSFET 2 is connected to the earth, thus constituting a complementary MOS (hereinafter referred to as CMOS) inverter 30a. Likewise, the P-channel MOSFET 3 and the N-channel MOSFET 4 constitute a CMOS inverter 30b. With these two inverters 30a and 30b a bistable circuit, that is, a flip-flop, is formed. More particularly, the outputs of the two inverters 30a and 30b are connected to the inputs of the mating inverters 30b and 30a. In other words, the drains of the P-channel MOSFETs 1 and 3, and of the N-channel MOSFETs 2 and 4 are connected to the gates of the N-channel MOSFETs 4 and 2, and of the P-channel MOSFETs 3 and 1, respectively. In this way a one bit memory cell 30 is constructed.
The N-channel MOSFETs 6 and 7 which are used for transfer gates to control the writing-in and the reading-out operation, have drains (or sources) connected to the drain of the MOSFETs 1 and 2, and that of the MOSFETs 3 and 4, respectively, and have sources (or drains) connected to bit lines 8 and 9 respectively, which function as information lines for writing-in as well as reading-out. The gates of the N-channel MOSFETs 6 and 7 are connected to a word line 10 which functions as a selector line for writing-in as well as reading-out.
The sources and gates of the N-channel MOSFETs 11 and 12 are connected to power supply terminals 5, and their drains are connected to the bit lines 8 and 9. An information input signal line 13 is connected to the gates of the P-channel MOSFET 14 and N-channel MOSFET 15, which constitute a writing-in circuit 40. In addition, the information input signal line 13 is connected to the drain (or source) of the N-channel MOSFET 16, which is used for a gate to control the information to be written in. The source (or drain) of the MOSFET 16 is connected to the bit line 9, and its gate is connected to a writing-in control signal line 17 which is designed to control the writing operation of the memory cell 30. The drains of the MOSFETs 14 and 15 are connected to the drain (or source) of the N-channel MOSFET 18, which is used for a gate to control the data to be written in. The source (or drain) of the N-channel MOSFET 18 is connected to the bit line 8, and its gate is connected to the writing-in control signal line 17. In this way the MOSFETs 16 and 18 can transmit the output from the writing-in circuit 40 to the bit lines 8 and 9 through between the drain and source thereof.
In operation, the memory cells 30 and the MOSFETs 6, 7 are arrayed in matrix in plurality. A desired memory cell is directly selected by the random access method, in or from which memory cell the data is written or read out. While the memory cell stores data, the word line 10 is kept at almost zero voltage, thereby turning off the MOSFETs 6 and 7. The memory cell 30 constituted by the MOSFETs 1, 2, 3 and 4 is electrically separated from the bit lines 8 and 9. The memory cell 30 is in one of two stable states when the gates of the MOSFETs 1 and 2 are kept "L" (low). At this time the MOSFET 1 is in ON state with its drain being kept "H" (high). Accordingly, the gates of the MOSFETs 3 and 4 become "H", thereby turning on the MOSFET 4 with placing its drain "L".
When the memory cell 30 is in this stable state, information can be written therein by applying voltage corresponding to the information to the bit lines 8 and 9, and applying the voltage "H" to the word line 10 so as to address the memory cell 30.
Now, suppose that the logic "1" is to be written in the memory cell 30. The voltage "H" is applied to the writing-in control signal line 17, thereby turning on the MOSFETs 16 and 18, and the voltage "H" corresponding to the logic "1" is applied to the information input signal line 13. In this way the bit line 9 is kept "H" through the MOSFET 16. In addition, the gates of the MOSFETs 14 and 15 are kept "H", thereby turning off the MOSFET 14 and turning on the MOSFET 15. Thus the drains of the MOSFETs 14 and 15 become "L", thereby placing the bit line 8 "L" through the MOSFET 18.
At this stage, when the word line 10 is placed 37 H38 , the MOSFETs 6 and 7 are turned on, thereby enabling the potentials in the bit lines 8 and 9 to be impressed on the memory cell 30. As a result, the MOSFET 1 is turned off whereas the MOSFET 2 is turned on, thereby reversing the states of the MOSFETs 1, 2, and 3, 4. In this way the memory cell 30 enters into the other stable state which means storing the information "1". Subsequently, the word line 10 and the writing-in control signal line 17 are returned to "L". With this the writing operation ends.
When information is to be read out from the memory cell 30, voltage of the same amplitude as that applied while writing-in operation, is impressed on the word line 10, thereby turning on the MOSFETs 6 and 7. This ensures that the electric charges stored in the bit lines 8 and 9 through the MOSFETs 11 and 12 are absorbed by the information stored in the memory cell 30, whereby a potential difference is given to between the bit lines 8 and 9 in accordance with the information stored in the memory cell 30. In this way the stored information is transmitted to the bit lines 8 and 9, and thereafter it is amplified as by a sense amplifier, and is output to the outside.
When this reading operation is to be performed, it is the common practice to pre-charge the bit lines 8, 9 to the "H" voltage through the MOSFETs 11, 12. This is important in preventing an erroneous writing of the information in the bit lines onto the memory cell, which is likely to occur when the MOSFETs 6, 7 are turned on in a situation where the bit lines, having a large parasitic capacity, have information opposite to that stored in the memory cell.
Under the prior art semiconductor memory device mentioned above, the bit lines are constantly charged in spite of the fact that the charging-up is required only when a reading-out operation is to be performed. As a result, the writing information and the electric charges in the bit lines come into collision when information is to be written in. This increases the consumption of electricity, and slows down the operational speeds.
One of prior art methods of controlling the writing and the reading operation is a technique disclosed in the article entitled "4K Static 5 V RAM" by Jeffrey M. Schlageter, Nagab Jayakumar, Joseph H. Kroeger and Vahe Sarkissian, which was prepared for the 1976 International Solid-State Circuit Conference. The article teaches that by disabling the Chip Enable signal, the bit and data lines are equalized to an intermediate voltage of the power supply voltage.